The present invention relates to electrical circuits, and, more particularly, to an emitter-coupled logic circuit applicable to gate array design.
Gate arrays are semiconductor devices with standard doping layers and customizable metalization layers. Gate arrays allow a design effort to obtain application specific integrated circuits while avoiding the long lead times involved in designing a circuit from scratch. Since they are neither off-the-shelf items, nor entirely customized, gate arrays are considered semi-custom devices. Gate arrays can be fabricated according to a variety of process technologies, for example, complementary metal-on-oxide (CMOS) and bipolar emitter-coupled logic (ECL).
To facilitate the customizing of a gate array, the gate array is divided into a number of transistor groupings or "cells". A cell library is often made available which defines macros, each of which corresponds to a logic function or combination of functions which can be implemented in a predetermined number of cells or fractions thereof. In some gate array designs, a given function may be implemented many times. Thus, given the competitive condition of the gate array industry, it is a commercial necessity to implement each logic function as efficiently as possible to maximize the functionality of the completed gate array design. To a first approximation, efficient implementation means minimizing transistor count and the number of current sources for a given number of gating levels.
When high speeds are required, ECL is often the process of choice. Rather than switching current on and off, ECL circuits redirect a constant magnitude network current through alternate paths. Transistors in an ECL circuit remain in their linear operating regions and, accordingly, are not subject to the delays involved in switching in and out of saturation.
A typical ECL circuit includes a voltage source, a current network and a gating system. The voltage source is generally considered as separate high (VCC) and low (VEE) sources. The voltage source applies a potential difference across the network so as to generate a current through one, or sometimes more, of the paths that constitute the network. The gating system determines the path or paths through which the network current flows at any given time.
An elementary gate includes a "switching" transistor and a "reference" transistor, which are characterized by the voltages applied to their bases. The voltage applied to the base of a "reference" transistor is a constant reference voltage (VBB), usually between VCC and VEE. The voltage applied to the base of a "switching" transistor is usually discretely variable between a voltage above VBB and a voltage below VBB.
The elementary gate's switching and reference transistors have their emitters coupled, hence the designation "emitter-coupled logic", and their collectors uncoupled. "Coupled" implies the existence of a conductive path between coupled elements. Whether a conductive path is coupling depends on the operational significance of any voltage drops along the path. If current through the path undergoes a voltage drop comparable to, e.g. is one third or more of, that which the same current would undergo through a transistor, there is no coupling, and the elements electrically connected by the path are "uncoupled", as the term is used herein. If the resistance is such that the voltage drop caused by an operational current is substantially less than, e.g. less than one tenth, that the same current would undergo through a transistor, then elements connected by the path are considered "coupled".
The operation of this elementary gate in the context of a circuit with a voltage applied across the gate is straightforward. When the voltage at the base of the switching transistor is below the reference voltage VBB, current flows from the high voltage source, through the reference transistor via its respective load resistor and eventually to the low voltage source. Alternatively, when the voltage applied to the base of the switching transistor is higher than the reference voltage VBB, current flows through the switching transistor. Thus, the gating system, by controlling the voltage at the base of the switching transistor determines the path of the current through the gate.
Where a load resistance is placed in series between the high voltage source and the collector of the reference transistor, a low voltage at the base of the switching transistor causes a voltage drop across the load resistor; no such drop occurs when the voltage at the base of the switching transistor is high. Accordingly, the voltage at the base of the switching transistor can control an output driven by the voltage between the load resistor and the collector of the reference transistor. Analogous effects can be achieved by incorporating a load resistor between the high voltage source and the collector of the switching transistor.
A common approach to elaborating upon the elementary gate is to place a second switching transistor in parallel with the first to produce an OR gate. In such an OR gate, the voltages at the bases of the switching transistors are the inputs, while the output is provided by a voltage between a load resistor and the collector of the reference transistor, or the coupled collectors of the parallel switching transistors.
Such gates are incorporated into current networks. Typically, each current is characterized by an electron current source transistor through which substantially all of the network current flows. Networks can be characterized according to the number of gating levels involved. A one-level series gating network might include the OR gate described above with the gate emitters coupled to the collector of the source transistor. In a two-level series gating network, the sources of current at the collectors of the reference transistor and the switching transistors would be determined by another set of gates electrically between the OR gate and the high-voltage source. Higher level series gating structures can be generated by extension.
Multi-level series gating networks include subnetworks as well as current paths. A subnetwork is constituted by a set of one or more network current paths which share a transistor which defines the subnetwork. The "subnetwork" transistor of a given network is defined to be the common transistor at the lowest voltage level in the constituting paths other than the network current source transistor and the defining transistors of any subnetworks which include the given network. Subnetworks on the same level are mutually exclusive in the sense that a given path must belong to one and only one subnetwork on a given level.
Conventionally, network current flows through only one network path, in other words, through one series of transistors, at a time. An exception is illustrated by the OR gate, since when both inputs are on, substantial current can flow through both switching transistors, if their specifications are relatively close. The division of the current between the switching transistors is not operationally significant, since if the current only passes through one of the switching transistors, the effect on the output is the same.
The ECL gate array industry, like many others, has developed certain design principles which are intended to facilitate the design of logic functions. However, such design principles can serve to exclude approaches which in some cases can yield more optimal results. As described hereinbelow, some common design assumptions are eschewed to implement certain logic functions more efficiently.